1. Field of the Invention
The invention relates to a semiconductor structure and fabrication method thereof, and more particularly, to a semiconductor structure with better quality epitaxial layer.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
Nevertheless, conventional FinFET fabrication of forming recesses after removing part of fin-shaped structures to accommodate the growth of epitaxial layer typically causes the fin-shaped structures to be lower than the surrounding shallow trench isolation (STI) as a result of over-etching, thereby influencing the formation of epitaxial layer afterwards. Hence, how to improve the current FinFET fabrication process for resolving this issue has become an important task in this field.